1. Field of the Invention
This invention relates to analog-to-digital (A/D) converter systems of the cascaded multi-stage type wherein each stage is a parallel converter, and develops a corresponding part of the final digital output signal. More particularly, this invention relates to such converters wherein one or more stage has extended range to provide for error correction.
2. Brief Description of the Prior Art
Parallel or "flash" converters of various designs have been available for some time, and have speed of conversion as their principal goal. One design approach is to employ a successive series of such stages (or cycles of operation) each arranged to develop a digital output of limited scope, e.g., 3 or 4 bits, and to produce from each stage (or cycle of operation) an analog residue signal representing the difference between the analog input and the quantized approximation made by the previous stage. This residue signal is the input for the next stage (or cycle). An example of this kind of converter is shown in U.S. Pat. No. 4,814,767 (Fernandes et al).
In a later design, shown in U.S. Pat. No. 5,184,130 issued on Feb. 2, 1993 to the present inventor, the first stage of the converter develops two analog residue signals for the second stage. These two residue signals represent the differences between the analog input signal and the two first-stage flash converter thresholds (or "quantization levels") which are respectively above and below the analog input signal. The sum of these two residue signals is equal to one LSB of the first-stage flash converter. Both of these two residue signals are amplified by respective interstage amplifiers. The second flash stage uses the amplified sum of these two residues as its reference signal, thus defining the required full-scale range of the second flash stage.
It is desired to provide such a converter with error correction capability, such as disclosed in the above Fernandes patent, wherein the range of one (or more) stages is extended beyond its nominal range. Such additional range is sometimes referred to as "error correction range", "overlap", or "redundancy". However, in the two-residue architecture, providing such additional range presents a problem, since there is no "reference signal" in the usual sense, and thus error correction cannot be achieved simply by using a larger reference signal. An alternative way of achieving this effect of an increased range is shown in U.S. Pat. No. 5,151,700 (Matsuzawa et al). That scheme however requires developing three signals from the first stage and introduces undue complexity.